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FEDL7051LA-02
1 Semiconductor ML7051LA
Bluetooth Baseband Controller IC
This version: Sept. 2000
GENERAL DESCRIPTION
The ML7051LA is a CMOS digital IC for use in 2.4 GHz band Bluetooth systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Used in conjunction with the ML7050LA (Bluetooth RF Transceiver IC) and the OKI Bluetooth Protocol Stack Software, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems.
FEATURES
* * * * * * * * * Conforms to the Bluetooth Specification (Ver1.0B) The ARM7TDMI is installed as the CPU (operation at a maximum of 32 MHz in this LSI) 1-Ch, 16-bit auto-reload timer Interrupt controller (17 causes) Built-in 8 kbyte, 4-Way Copy Back Unified Cache Built-in 24 kbyte RAM (supports 16-byte burst access) Up to a total of 2 Mbyte of SRAM, ROM, and Flash ROM can be connected to the external memory bus. PCM-CVSD transcoder is installed. Installed interfaces: - UART(*) interface (up to 921.6 kbps) - USB(*) interface (conforms to USB1.1) - UART synchronous serial port interface - General-purpose I/O interface (programmable interrupts) - PCM interface (PCMLinear/A-law/-law can be selected) - JTAG interface (*) This mark indicates interfaces that support the HCI command. * Power supply voltages: For I/O: 3.0 to 3.6 V; for internal core: 2.25 to 2.75 V * Package: 144-pin BGA (P-LFBGA144-1111-0.80) (Dimensions: 11 mm x 11 mm x 1.5 mm; pin pitch: 0.8 mm)
ARM and the ARM POWERED logo are registered trademarks of ARM Ltd., UK. ARM7TDMI and Thumb are trademarks of ARM Ltd., UK. The information contained herein can change without notice owing to the product being under development.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Allowable power dissipation Storage temperature Symbol VDD VI Pd Tstg Conditions -- -- -- -- Rating -0.3 to +4.5 -0.3 to +4.5 1.35 -55 to 150 Unit V V W C
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage (for I/O) Power supply voltage (for the internal core) "H" level input voltage "L" level input voltage Operating temperature Symbol Vdd_io Vdd_core Vih Vil Ta Conditions -- -- -- -- -- Min. 3.0 2.25 2.2 0 -40 Typ. 3.3 2.5 -- -- -- Max. 3.6 2.75 3.6 0.8 85 Unit V V V V C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Vdd_io = 3.3 V 0.3V, Vdd_core = 2.5 V 10%, Ta = 0 to 70C) Parameter "H" level output voltage "L" level output voltage Input leak current Output leak current Power supply current (during operation) Power supply current (during stand-by) Symbol Voh Vol Ii Io Iddo Idds Conditions Ioh = -4 mA Iol = 4 mA Vi = GND to 3.6 V Vo = GND to Vdd During 32 MHz operation CLK Stopped Min. 2.4 -- -10 -10 0 -- Typ. -- -- -- -- 50 50 Max. -- 0.4 10 10 70 500 Unit V V A A mA A
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PIN PLACEMENT
1 NC A CIO13 B CIO11 C CORE_ VDD D CIO7 E CIO4 F GND G MA15 H MA12 J MA10 K GND L MA6 M NC N MA5 MA3 CORE_ VDD MD15 MD12 MD8 MD3 GND MWEn MCSn1 MBSn0 NC MA7 MA1 GND MD13 MD11 MD10 MD5 MD4 MD1 MREn MBSn1 GND MA9 MA4 MA2 MA0 VDD GND ND7 CORE_ VDD MD0 MOEn1 TDO CORE_ VDD MA13 CORE_ VDD MA8 MD14 GND MD9 MD6 MD2 MCSn0 MOEn0 TMS CLK MA16 MA11 MA14 TEST_L TEST_L PLLSEL nTRST PLLEN TCK MA17 MA19 MA18 SVCO0 CORE_ TEST_O SVCO1 DPLOUT VDD VDD CIO0 GND GND DP VDD DM CIO3 CIO1 CIO2 GND PUCTL VDD A_VDD CIO5 CIO9 CIO6 A_GND RXD SCLK12 XCLK CIO8 CIO10 PCMOUT PLL_ DATA PLL_ PLLLOCK POW RSSI_ CLK CORE_ VDD RSSI GND VDD TXC_IN GND CIO12 PCMCLK RXC GND PLL_OF TX_POW TEST_L BBWSEL TXCSEL CORE_ RESETn TEST5 VDD CIO15 CORE_ PLL_PS VDD GND PLL_CLK RX_POW TEST_L TEST_L TEST_L TEST0 TEST2 TEST4 GND TDI REMAP1 2 CIO14 3 PCMIN 4 PCM SYNC 5 TXD 6 PLL_LE 7 VDD 8 9 10 11 12 13 NC
TEST_L TEST_L TEST1 TEST3
VTM SCLKSEL REMAP0
TOP VIEW
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PIN DESCRIPTIONS
RF I/F
Pin Name TXD RXD PLL_DATA PLL_CLK PLL_LE PLL_OFF RSSI RSSI_CLK PLL_POW TX_POW RX_POW PLL_PS PLLLOCK RXC I/O O I O O O O I O O O O O I O Internal Pull Up/Down -- -- -- -- -- -- Pull down -- -- -- -- -- Pull down -- Initial Value -- -- L L L L -- -- H H H L L L Pin Placement A5 E11 D5 B6 A6 C7 D10 D8 D7 C8 B7 B4 D6 C5 Description Transmit data output (To ML7050LA Pin# A8) Receive data input (To ML7050LA Pin# H5) PLL setting data output (To ML7050LA Pin# H3) PLL setting clock output (To ML7050LA Pin# G3) PLL setting load enable output (To ML7050LA Pin# H4) PLL Open-loop/Closed-loop control signal output (To ML7050LA Pin# G8) Receive field strength data input (To ML7050LA Pin# G6) RSSI transfer clock (To ML7050LA Pin# H8) Local transmit circuit power control signal output (To ML7050LA Pin# A7) Transmit power control signal output (To ML7050LA Pin# B6) Receive power control signal output (To ML7050LA Pin# B3) PLL power control signal output PLL lock signal input Bluetooth receive clock output (1 MHz) Bluetooth transmit clock input (1 MHz) TXC_IN I Pull down L D13 When the transmit clock is used by a clock (RXC) that is generated from the receive data, set TXCSEL(Pin# C11) to H and connect to RXC(Pin# C5). Bluetooth transmit clock setting pin TXCSEL I Pull down L C11 L: Select 1 MHz divided by internal PLL. H: Select TXC_IN input signal.
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CLK and Configuration
Pin Name SCLK12 XCLK SCLKSEL RESETn BBWSEL REMAP0 I/O I I I I I I Internal Pull Up/Down -- -- Pull down -- -- -- Initial Value -- -- -- -- -- -- Pin Placement E12 E13 A11 C13 C10 A12 Description Master clock (12 MHz) input pin (Power level: CMOS level) User clock input pin System clock select pin L: Select CLK divided by internal PLL H: Select XCLK input signal Hardware reset pin (Reset = L) BANK0 region bit width select pin L: 8-bit H: 16-bit REMAP select pin during boot up REMAP[1:0] = "00" Reserved "01" Stacked Flash ROM "10" External MCS[1] device "11" External MCS[0] device
REMAP1
I
B13
Memory I/F
Pin Name MA[19:0] MD[15:0] MWEn MREn MCSn0 MCSn1 MBSn0 MBSn1 MOEn0 MOEn1 MWAIT I/O O I/O O O O O O O O O I Internal Pull Up/Down -- -- -- -- -- -- -- -- -- -- -- Initial Value L Z H H H H H H H H -- Pin Placement [*1] [*2] N10 M11 K10 N11 N12 M12 K11 L11 F3 Description External address bus External data bus External write enable signal output External read enable signal output External RAM space chip select External I/O space chip select External lower byte select External upper byte select External MCS[0] device output enable (MCSn0 and WREn OR output) External MCS[1] device output enable (MCSn1 and WREn OR output) External wait signal input (Pin shared with GPIO1)
[*1]
MA19: H3; MA18: H4; MA13: K2; MA12: J1; MA6: M1; MA5: N2; MD15: N5; MD14: K5; MD9: K7; MD8: N7; MD2: K9; MD1: M10;
MA17: H2; MA11: J3; MA4: L3; MD13: M5; MD7: L8; MD0: L10
MA16: J2; MA10: K1; MA3: N3; MD12: N6; MD6: K8;
MA15: H1; MA14: J4 MA9: L2; MA8: K4; MA2: L4; MA1: M3; MD11: M6; MD10: M7 MD5: M8; MD4: M9;
MA7: M2 MA0: L5
[*2]
MD3: N8;
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USB I/F
Pin Name DP DM PUCTL VBUS (GPIO0) I/O I/O I/O O I Internal Pull Up/Down -- -- -- -- Initial Value Z Z L -- Pin Placement G11 G13 F11 G3 USB data USB data Pull-up control pin USB detection pin Description
UART I/F
Pin Name SOUT SIN DCD RTS CTS DSR DTR RI I/O O I I O I I O I Internal Pull Up/Down -- -- -- -- -- -- -- -- Initial Value H -- -- H -- -- H -- Pin Placement B2 A2 B1 C3 C1 D3 E3 D2 Description ACE transmit serial data (Pin shared with GPIO15) ACE receive serial data (Pin shared with GPIO14) Data carrier detection (Pin shared with GPIO13) ACE transmit data ready (Pin shared with GPIO12) ACE transmit ready (Pin shared with GPIO11) Receive data ready (Pin shared with GPIO10) Receive ready (Pin shared with GPIO9) Ring indicator (Pin shared with GPIO8)
SIO I/F
Pin Name STXD SRXD STDCLK SRDCLK I/O O I I/O I/O Internal Pull Up/Down -- -- -- -- Initial Value H -- -- -- Pin Placement E1 E4 E2 F1 Description Serial data output (Pin shared with GPIO7) Serial data input (Pin shared with GPIO6) Clock for serial data output, in the input state after initialization (Pin shared with GPIO5) Clock for serial data input, in the input state after initialization (Pin shared with GPIO4)
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PLAT_SIO I/F
Pin Name UTXD URXD I/O O I Internal Pull Up/Down -- -- Initial Value H -- Pin Placement F2 F4 Description Serial data output (Pin shared with GPIO3) Serial data input (Pin shared with GPIO2)
GPIO I/F
Pin Name GPIO[15:0] I/O I/O Internal Pull Up/Down -- Initial Value -- Pin Placement [*3] Description Parallel I/O data (in the input state after initialization)
JTAG I/F
Pin Name TDI TDO nTRST TMS TCK I/O I O I I I Internal Pull Up/Down Pull down -- Pull down Pull down Pull down Initial Value -- L -- -- -- Pin Placement B12 L12 J11 K12 J13 Serial data input Serial data output Reset pin Mode setting pin Serial data clock Description
PCM I/F
Pin Name PCMOUT PCMIN PCMSYNC I/O O I I/O Internal Pull Up/Down -- Pull down Pull down Initial Value L -- -- Pin Placement D4 A3 A4 PCM data input PCM sync signal (8 kHz), in the input state after initialization (can be switched by an internal register) PCM clock (64 kHz/128 kHz), in the input state after initialization (can be switched by an internal register) Description PCM data output
PCMCLK
I/O
Pull down
--
C4
[*3]
CIO15: CIO14: CIO13: CIO12: CIO11: CIO10: CIO9: CIO8: CIO7: CIO6: CIO5: CIO4: CIO3: CIO2: CIO1: CIO0:
B2 A2 B1 C3 C1 D3 E3 D2 E1 E4 E2 F1 F2 F4 F3 G3
GPIO15/SOUT (UART I/F) GPIO14/SIN (UART I/F) GPIO13/DCD (UART I/F) GPIO12/RTS (UART I/F) GPIO11/CTS (UART I/F) GPIO10/DSR (UART I/F) GPIO9/DTR (UART I/F) GPIO8/RI (UART I/F) GPIO7/STXD (SIO I/F) GPIO6/SRXD (SIO I/F) GPIO5/STXDCLK (SIIO I/F) GPIO4/SRXDCLK (SIO I/F) GPIO3/UTXD (UPLAT_SIO I/F) GPIO2/URXD (UPLAT_SIO I/F) GPIO1/NWAIT (Memory I/F) GPIO0/VBUS (USB I/F)
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TEST I/F
Pin Name TEST_L TEST_O SVCO0 SVCO1 VTM CLK NC I/O I O I I I O -- Internal Pull Up/Down -- -- -- -- -- -- -- Initial Value -- L -- -- -- -- -- Pin Placement [*4] H13 H10 H12 A10 K13 A1, A13 N1, N13 Test pin (input) Test pin (output) Built-in PLL characteristics setting pin Built-in PLL characteristics setting pin Built-in Flash ROM test pin Built-in Flash ROM test pin No Connection Description
Power, GND
Pin Name VDD CORE_VDD GND A_VDD A_GND I/O -- -- -- -- -- Internal Pull Up/Down -- -- -- -- -- Initial Value -- -- -- -- -- Pin Placement [*5] [*6] [*7] F13 E10 Description I/O power pin 3.3 V 0.3 V Core power pin 2.5 V 10% Digital block ground pin Analog block power pin 2.5 V 10% Analog block ground pin
[*4]
[*5] [*6] [*7]
TEST_L (TEST5): C9 TEST_L (TEST4): B10 TEST_L (TEST3): A9 TEST_L (TEST2): B9 TEST_L (TEST1): A8 TEST_L (TEST0): B8 TEST_L (PLLSEL): J10 TSET_L (PLLEN): J12 A7, D12, F12, G2, G12, L6 B3, C12, D1, D9, H11, K3, L9, L13, N4 B5, B11, C2, C6, D11, F10, G1, G4, G10, K6, L1, L7, M4, M13, N9
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1 Semiconductor
BLOCK DIAGRAM
SIO I/F
CLK GEN AMBA APB
Default Slave 16 I/F AMBA AH I/F WDTB I/F AMBA APB I/F USB PIO I/F SIO I/F I/F I/F I/F UART I/F I/F CTL/ WDT IRC Arbiter TIC ARM7 TDMI Cache/ Bus I/F
ML7051LA
APB Ctl I/F
Clock 24 kB RAM Timer SIO APB Ctl System Control XMC(BIU) 8 Mbit SRAM 8 Mbit Flash ROM I/F I/F PCM/ CVSD BT-BB Core
RF LSI
PIO I/F
SIO I/F
USB I/F
UART I/F
PCM Codec
FEDL7051LA-02
ML7051LA
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DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block * Generates from the SCLK12 (12 MHz) clock that is supplied to each block * STOP/HALT function * External clock selection function CTL/WDT Block * * * * * * * * Control of the frequency division function of the internal main clock Control of clock supplied to each peripheral Control of reset of each peripheral STOP/HALT control External clock selection control CIO switching function Watchdog timer function (interrupt/reset) 3 count stop functions
WDTB Block * Watchdog timer function (interrupts only) * 3 count stop functions Baseband Core Block
RF LSI Tx SCO Buffer Audio Codec I/F Tx ACL Buffer Packet Composer TXD
Security APB ARM I/F Rx SCO Buffer Rx ACL Buffer
Timing
FHCNT
RF CNT
CNT
Packet Decomposer
RXD
* RF Controller - RF power supply control (PLL, TX, RX) - Local PLL frequency division ratio setting - Receive clock regeneration function - Synchronization detection (synchronizing within the permissable error limit of SyncWord) - Receive clock re-timing function * FH Controller hopping - Sequence control - Frequency hopping selection function - CRC computation's initial value selection function
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* Timing Generator - Bluetooth clock generation - Operation interrupts depend on mode (slot, scan, sniff, hold, park) - Sync detection timing generation (sync window 10 s) - PLL setting timing generation - Transmit/Receive timing generation - Multi-master timing management function * Packet Composer - Access code generation (SyncWord generation, appending PR*TRAILER) - Packet header generation (HEC generation, scrambling, FEC encoding) - Payload generation (CRC generation, encryption, scrambling, FEC encoding) - Packet synthesis * Packet Decomposer - Packet decomposition (separating the packet header and the payload) - Packet header processing (FEC decoding, descrambling, HEC error detection, header information separation) - Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload separation) * Security - Various key generation functions (initialization, link key, encryption key) - Certification function - Encryption function USB Block * * * * * * Conforms to USB standard Ver. 1.1. Supports 12 Mbps transfer Supports four data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer) Built-in USB transceiver circuit 5 or 6 built-in end points, and built-in FIFO for data storage 8-, 16-, 24-, 32-bit read/write is possible for the FIFOs of EP0 to EP5 (with byte control)
UART Block * * * * * * * * * * Full-duplex buffering method All status reporting function Built-in 64-byte transmit/receive FIFO Modem control based on CTS, DCD, and DSR Programmable serial interface 5-, 6-, 7-, 8-bit characters Generation and verification of odd parity, even parity, or no parity 1, 1.5, or 2 stop bits Programmable Baud Rate Generator (1200 bps to 921.6 kbps) Error servicing for parity, overrun, and framing errors
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SIO Block * UART/Synchronous type serial port interface * UART Mode: - Data length: can be selected as 7 or 8 bits - Supports odd parity, even parity, or no parity - Error servicing for parity, overrun, and framing errors - Supports 1 or 2 stop bits - Full-duplex communication is possible * Clock synchronization mode: - Data length: can be selected as as 7 or 8 bits - Error servicing for overrun errors - Full-duplex communication is possible PLAT-SIO Block * * * * * * * Start-stop synchronization type serial port interface Built-in dedicated baud rate generator Data length of 7 or 8 bits can be selected 1 or 2 stop bits can be selected. Supports odd or even parity Error servicing for parity, overrun, and framing errors Full-duplex communication is possible
PCM-CVSD Transcoder Block * Application side I/O: - PCM Codec - APB-Bus (USB) * Application-side format: - PCM linear (8, 16 bits/sample, 64 kHz sampling frequency)/A-law/-law * Bluetooth-side format: - CVSD/A-law/-law * All combinations of the above conversions are supported * PCMSYMC/PCMCLK I/O can be switched (in the input state after initialization) GPIO Block * * * * * All 16 bits Input/Output selection possible for each bit Interrupts can be used for all 16 bits Interrupt masks and interrupt modes can be set for all bits In the input state immediately after a reset
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APPLICATION NOTES
Operation During Boot Up * Remapping during boot up is performed according to external pins REMAP[1:0]. REMAP1 L L H H REMAP0 L H L H : : : : Reserved Stack Flash ROM Devices connected to external MCS[1] Devices connected to external MCS[0]
* Bit width that corresponds to BANK0 during boot up is set according to external pin BBWSEL. BBWSEL = L : 8-bit BBWSEL = H : 16-bit Clock Selection * The CPU clock supply source is selected according to external pin SCLKSEL. SCLKSEL = L : Use 32/16/8/4 MHz clock that was divided down from the internal PLL output of 192 MHz that was generated from external pin SCLK12 (12 MHz). (Initial value is 32 MHz.) SCLKSEL = H : Use external pin XCLK. Note: The clock supply source can also be set by the CLKCNT register in the CTL/WDT block. * Bluetooth transmission clock is selected according to external pin TXCSEL. TXCSEL = L : Use 1 MHz clock that was divided down from the internal PLL output (192 MHz). TXCSEL = H : Use external pin TXC_IN. Note: This clock can also be set by the CLKCNT register in the CTL/WDT block. HCI Transport Selection * HCI is selected (USB/UART) according to the logical value of GPIO0 at initial powerup of ML7051LA. GPIO0 = L GPIO0 = H : UART is used as HCI. : USB is used as HCI.
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USB Peripheral Circuit * Please refer to the following peripheral circuit example when using USB.
3.3 V
ML7051LA
GPIO0 G3
47 k
PUCTL DP DM
F11 G11 G13
1.5 k 16 16 D+ (3.3 V) D- (3.3 V)
Setting the UART Baud Rate * Use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands to set the UART baud rate. Available baud rate settings: 1200/2400/4800/7200/9600/19.2K/38.4K/56K/57.6K/115.2K/230.4K/345.6K/460.8K/921.6K (Initial value is 115.2 kbps.) Setting the PCM-CVSD Transcoder * Please use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands in HCI to set the PCM-CVSD transcoder parameters. * It is possible to set the following parameters using the VCCTL command: - PCMSYNC/PCMCLK mode (in the input state after initialization) - Mute reception (initial setting: OFF) - Mute transmission (initial setting: OFF) - Air coding CVSD (initial setting)/-law/A-law - Interface coding Linear (initial setting)/-law/A-law - PCM format (data width of one PCM Linear sample) 8-bit (initial setting)/14-bit/16-bit - Serial interface format Short frame (initial setting)/long frame - Application interface mode PCM Codec I/F (initial setting)/APB I/F
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External Memory * ML7051LA specifications for the devices that are connected to MCS[0] and MCS[1] are explained below. * When connected to MCS[0] device: - 1 memory bank - Bus width: 8 or 16 bits - Byte access control: BS/WE - Supported devices: Normal SRAM, Flash Memory, Page mode Flash memory Bus timing to MCS[0] device
MREn MWEn XA MCSn0 MBSn* XD_I (read) XD_O (write) 1 or 2 clocks [*1] [*2] 1 or 2 clocks 1 clock fixed [*1]
[*1]
[*2]
Access time: 3, 4, 5, 6, 7, 8 clock cycles (including one clock cycle for set-up) 6, 8, 10, 12, 14, 16 clock cycles (including two clock cycles for set-up) Data OFF time: 1, 2, 3, 4 clock cycles
Note: Oki software settings: - Insert the maximum wait immediately after reset. - Page mode: OFF - During operation (32 MHz operation), Access time: 3 clock cycles Data OFF time: 1 clock cycle Note: A device with an access time of 120 nsec or less is recommended.
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* When connected to MCS[1] device: - 1 memory bank - Bus width: 8-bit or 16-bit - Byte access control: BS/WE Bus timing to MCS[1] device (IOWRTYPE = 0)
MREn MWEn XA MCSn1 MBSn* XD_I (read) XD_O (write) [*3] [*1] [*2] 1 clock fixed [*3] [*1]
Bus timing to MCS[1] device (IOWRTYPE = 1)
MREn MWEn XA MCSn1 MBSn* XD_I (read) XD_O (write) [*1] [*3] [*2] 1 clock fixed 1 clock fixed [*3] [*4] [*1]
[*1]
[*2] [*3] [*4]
Access time: 2, 4, 8, 16, 32 clock cycles (including one clock cycle for set-up) It is only possible to use the external pin nWAIT then insert a wait period of 16 x n clock cycles when the 16 cycle clock is selected. Data OFF time: 1, 2, 3, 4 clock cycles Address set-up time: 1, 2, 3, 4 clock cycles Write data set-up time: 0 clock cycles (IOWRTYPE = 0) 0, 1, 2, 3 clock cycles (IOWRTYPE=1)
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* Relationship between address set-up time and write data set-up time (when IOWRTYPE = 1) - Address set-up time: 1 clock cycle (write data set-up: 0 clock cycles) 2 clock cycles (write data set-up: 1 clock cycle) 3 clock cycles (write data set-up: 2 clock cycles) 4 clock cycles (write data set-up: 3 clock cycles) Note: Oki software settings: - Insert the maximum wait immediately after reset. - IOWRTYPE = 0 - During operation (32 MHz operation), Access time: 2 clock cycles Data OFF time: 1 clock cycle Address set-up time: 1 clock cycle Note: A device with an access time of 120 nsec or less is recommended. * Miscellaneous - MA0 is not used with devices that have a 16-bit data bus. Connect MA1 to device A0. (MA0 is Open.) - Connect MA0 to device A0 for devices that have an 8-bit data bus. - MOEn[0] is the AND signal for MCS[0] and MREn. Perform an open process when this is not in use. - MOEn[1] is the AND signal for MCS[1] and MREn. Perform an open process when this is not in use.
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Process when interface pins are unused * The following tables show the processes that are performed when interface pins are not used. RF I/F
Pin Name PLL_DATA PLL_CLK PLL_LE PLL_OFF PLL_POW TX_POW RX_POW RSSI RSSI_CLK PLL_PS PLLLOCK RXC TXC_IN TXCSEL Process When Pin Not Used Open Open Open Open Open Open Open Pull down to GND Open Open Pull down to GND Open Pull down to GND Pull down to GND Comments
Memory I/F
Pin Name Process When Pin Not Used When connected For 16-bit devices: * Open MA0. MA[19:0] Open * Connect from MA1 in order from A0 of the connected device. For 8-bit devices: * Connect to each corresponding address. MD[15:0] MWEn MREn MCSn0 MCSn1 MBSn0 MBSn1 MOEn0 MOEn1 MWAIT Open Open Open Open Open Open Open Open Open Refer to GPIO1 Only use when connecting to a device that has only one, but not both of CEn or REn. Comments
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USB I/F
Pin Name DP DM PUCTL VBUS (GPIO0) Process When Pin Not Used Open Open Open Pull down/GND Pull up to Vdd when using USB. Comments
UART I/F
Pin Name SOUT SIN DCD RTS CTS DSR DTR RI Process When Pin Not Used Refer to GPIO15 Refer to GPIO14 Refer to GPIO13 Refer to GPIO12 Refer to GPIO11 Refer to GPIO10 Refer to GPIO9 Refer to GPIO8 Comments
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SIO I/F
Pin Name STXD SRXD STDCLK SRDCLK Process When Pin Not Used Refer to GPIO7 Refer to GPIO6 Refer to GPIO5 Refer to GPIO4 Comments
PLAT_SIO I/F
Pin Name UTXD URXD Process When Pin Not Used Refer to GPIO3 Refer to GPIO2 Comments
GPIO I/F
Pin Name GPIO[0] GPIO[15:1] Process When Pin Not Used -- Pull down/GND Comments When using UART: Pull down to GND When using USB: Pull up to Vdd
JTAG I/F
Pin Name TDI TDO nTRST TMS TCK Process When Pin Not Used Open Open Open Open Open Comments
PCM I/F
Pin Name PCMOUT PCMIN PCMSYNC PCMCLK Process When Pin Not Used Open Open Open Open Comments
Processes of Other Pins TEST I/F, etc.
Pin Name TEST_L TEST_O SVCO0 SVCO1 VTM CLK NC Process When Pin Not Used GND Open Pull up to Vdd Pull down to GND Open GND Open Comments
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About the Oki Bluetooth Software * At Oki Electric Industry Co., Ltd., we have made available as Pack 1 the software protocol stack of the lower layer up to HCI that conforms to the Bluetooth Specification Ver. 1.0B for external Flash memory. Pack 1 contents: Baseband Controller, LMP, HCI. * We have also made available packs for the software protocol stack of the upper layer from HCI: Pack 2 (up to RFCOMM) and Pack 3 (including the Middleware). * Please contact Oki Electric Industry Co., Ltd. for more information regarding software contents, pricing, etc. Vender Specific Commands * Parameters can be set with the Pack 1 software by using the following Vendor Specific Commands. * Please contact Oki Electric Industry Co., Ltd. for more information. (1) HCI_VS_Write_BD_ADDR: Sets the BD address. (2) HCI_VS_Write_Country_Code: Sets the country code. (3) HCI_VS_Set_LC_Parameters: Sets the link control information. The following table shows the link control information that can be set.
Link Control Information Unit key Use unit key Channel count Minimum size of encryption key Maximum size of encryption key Appropriate size of encryption key PCM of SCO link 0: 2: 4: UART baud rate 6: 8: 9: Polling interval Initialization by MaskROM value 0: -law, 1: A-law, 2: Linear 1200 bps 4800 bps 9600 bps 38.4 kbps 57.6 kbps 230.4 kbps 1: 3: 5: 7: 9: 2400 bps 7200 bps 19.2 kbps 56 kbps 115.2 kbps 0: Do not use 1: Use Number of hopping channels Comments
10: 345.6 kbps 12: 921.6 kbps
11: 460.8 kbps
Unit: 625 sec
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FEDL7051LA-02
1 Semiconductor
ML7051LA
System Development Kit (SDK) * At Oki Electric Industry Co., Ltd., we have made available the System Development Kit (SDK) for the following objectives: - Software development of the upper Bluetooth layer - Overall system software - Device development with embedded ML7050LA or ML7051LA Please contact Oki Electric Industry Co., Ltd. for more information regarding System Development Kit contents, pricing, etc.
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FEDL7051LA-02
1 Semiconductor
ML7051LA
PACKAGE DIMENSIONS
(Unit: mm)
P-LFBGA144-1111-0.80
5
Notes for Mounting the Surface Mount Type Package
Package material Ball material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.3 TYP. 1/Aug.25,1999
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL7051LA-02
1 Semiconductor
ML7051LA
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd.
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